1. Field of the Invention
The present invention relates to a data distribution device for a memory device, and more particularly to a data distribution device which determines a scheme for distributing data applied when a write command is activated.
2. Description of the Prior Art
As generally known in the art, a synchronous memory device (such as a DDR SDRAM, a DDR2 SDRAM, etc.) receives and outputs data in synchronization with a clock signal. For example, in the case of a write operation in the DDR2 SDRAM, a write command and a column address are applied in synchronization with the rising edge of a clock signal, first data and second data are inputted in synchronization with the rising edge and the falling edge of the next clock signal, respectively, and then in a similar way, data as long as a burst length are continuously applied in synchronization with the rising edges and the falling edges of the clock signals consecutively following. Data continuously-applied as described above are inputted through each of data pins. For convenience of description, it is assumed that a memory device discussed in this document has a burst length of ‘4’.
Generally, in a write operation, 4-bit data (e.g., din0r<0>, din0f<0>, din1r<0> and din1f<0>), which have been sequentially (serially) applied through a specific data pin in synchronization with rising and falling edges of clock signals, are stored in four registers in one-to-one correspondence, and then are inputted to four input lines in one-to-one correspondence in synchronization with a clock signal. That is, the four registers function as a serial-to-parallel converter. The data din0r<0>, din0f<0>, din1r<0> and din1f<0> applied to the four input lines are transferred to four global input/output lines, respectively, and are then stored in a memory cell array. Herein, the data din0r<0>, din0f<0>, din1r<0> and din1f<0> represent data applied sequentially through a data pin DQ0 in synchronization with rising and falling edges of clock signals.
Meanwhile, before the four pieces of data are transferred to the global input/output lines, an operation of determining the sequence and positions for storing the four pieces of data in the memory cell array is performed. In this document, this operation is called ‘data distribution operation’ for convenience of description. Generally, the data distribution operation is determined according to a burst type and a starting column address. Herein, the burst type includes a sequential mode and an interleave mode, which are modes for determining a data application sequence. A starting column address used in this document represents the lowest two bits (A1 and A0) of a column address, which is also defined in the JEDEC standard. As generally known in the art, the above-mentioned four global input/output lines corresponds to the decoding values 0, 1, 2 and 3 of the starting column address, respectively. Therefore, data are transferred to the four global input/output lines in one-to-one correspondence according to the starting column address and the burst type.
Table 1 shows a data access sequence according to burst lengths, starting column addresses and burst types.
TABLE 1BurstStarting ColumnAccess SequenceLengthAddressSequential TypeInterleave Type2A000-10-111-01-04A1A0000-1-2-30-1-2-3011-2-3-01-0-3-2102-3-0-12-3-0-1113-0-1-23-2-1-08A2A1A00000-1-2-3-4-5-6-70-1-2-3-4-5-6-70011-2-3-4-5-6-7-01-0-3-2-5-4-7-60102-3-4-5-6-7-0-12-3-0-1-6-7-4-50113-4-5-6-7-0-1-23-2-1-0-7-6-5-41004-5-6-7-0-1-2-34-5-6-7-0-1-2-31015-6-7-0-1-2-3-45-4-7-6-1-0-3-21106-7-0-1-2-3-4-56-7-4-5-2-3-0-11117-0-1-2-3-4-5-67-6-5-4-3-2-1-0
FIG. 1 is a block diagram for explaining a conventional data distribution scheme. For reference, a 16-bit control signal ctr1<0:15>, which is applied to each latch section to control an operation of distributing input data, functions to determine a distribution sequence of 4-bit input data according to burst types and starting column addresses.
As shown in FIG. 1, 4-bit data din0r<0>, din0f<0>, din1r<0> and din1f<0> inputted sequentially through a data pin DQ0 are applied to a latch section 100. The latch section 100 transfers the data din0r<0>, din0f<0>, din1r<0> and din1f<0> to global input/output lines gio_0_0, gio_1_0, gio_2_0 and gio_3_0 in one-to-one correspondence according to logic levels of the 16-bit control signal ctr1<0:15>.
4-bit data din0r<1>, din0f<1>, din1r<1> and din1f<1> inputted sequentially through a data pin DQ1 are applied to a latch section 101. The latch section 101 transfers the data din0r<1>, din0f<1>, din1r<1> and din1f<1> to global input/output lines gio_0_1, gio_1_1, gio_2_1 and gio_3_1 in one-to-one correspondence according to logic levels of the 16-bit control signal ctr1<0:15>.
4-bit data din0r<2>, din0f<2>, din1r<2> and din1f<2> inputted sequentially through a data pin DQ2 are applied to a latch section 102. The latch section 102 transfers the data din0r<2>, din0f<2>, din1r<2> and din1f<2> to global input/output lines gio_0_2, gio_1_2, gio_2_2 and gio_3_2 in one-to-one correspondence according to logic levels of the 16-bit control signal ctr1<0:15>.
4-bit data din0r<3>, din0f<3>, din1r<3> and din1f<3> inputted sequentially through a data pin DQ3 are applied to a latch section 103. The latch section 103 transfers the data din0r<3>, din0f<3>, din1r<3> and din1f<3> to global input/output lines gio_0_3, gio_1_3, gio_2_3 and gio_3_3 in one-to-one correspondence according to logic levels of the 16-bit control signal ctr1<0:15>.
As shown in FIG. 1, according to the conventional data distribution device, each latch section receives a 16-bit control signal through 16 number of control lines in order to perform a distribution operation for 4-bit data applied to each latch section. For this reason, the conventional data distribution device has a problem in that a large layout area is required for disposition of control lines.